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Espressif Systems /ESP32-S2 /UART0 /INT_CLR

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Interpret as INT_CLR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (RXFIFO_FULL_INT_CLR)RXFIFO_FULL_INT_CLR 0 (TXFIFO_EMPTY_INT_CLR)TXFIFO_EMPTY_INT_CLR 0 (PARITY_ERR_INT_CLR)PARITY_ERR_INT_CLR 0 (FRM_ERR_INT_CLR)FRM_ERR_INT_CLR 0 (RXFIFO_OVF_INT_CLR)RXFIFO_OVF_INT_CLR 0 (DSR_CHG_INT_CLR)DSR_CHG_INT_CLR 0 (CTS_CHG_INT_CLR)CTS_CHG_INT_CLR 0 (BRK_DET_INT_CLR)BRK_DET_INT_CLR 0 (RXFIFO_TOUT_INT_CLR)RXFIFO_TOUT_INT_CLR 0 (SW_XON_INT_CLR)SW_XON_INT_CLR 0 (SW_XOFF_INT_CLR)SW_XOFF_INT_CLR 0 (GLITCH_DET_INT_CLR)GLITCH_DET_INT_CLR 0 (TX_BRK_DONE_INT_CLR)TX_BRK_DONE_INT_CLR 0 (TX_BRK_IDLE_DONE_INT_CLR)TX_BRK_IDLE_DONE_INT_CLR 0 (TX_DONE_INT_CLR)TX_DONE_INT_CLR 0 (RS485_PARITY_ERR_INT_CLR)RS485_PARITY_ERR_INT_CLR 0 (RS485_FRM_ERR_INT_CLR)RS485_FRM_ERR_INT_CLR 0 (RS485_CLASH_INT_CLR)RS485_CLASH_INT_CLR 0 (AT_CMD_CHAR_DET_INT_CLR)AT_CMD_CHAR_DET_INT_CLR 0 (WAKEUP_INT_CLR)WAKEUP_INT_CLR

Description

Interrupt clear bits

Fields

RXFIFO_FULL_INT_CLR

Set this bit to clear UART_THE RXFIFO_FULL_INT interrupt.
TXFIFO_EMPTY_INT_CLR

Set this bit to clear UART_TXFIFO_EMPTY_INT interrupt.
PARITY_ERR_INT_CLR

Set this bit to clear UART_PARITY_ERR_INT interrupt.
FRM_ERR_INT_CLR

Set this bit to clear UART_FRM_ERR_INT interrupt.
RXFIFO_OVF_INT_CLR

Set this bit to clear UART_UART_RXFIFO_OVF_INT interrupt.
DSR_CHG_INT_CLR

Set this bit to clear UART_DSR_CHG_INT interrupt.
CTS_CHG_INT_CLR

Set this bit to clear UART_CTS_CHG_INT interrupt.
BRK_DET_INT_CLR

Set this bit to clear UART_BRK_DET_INT interrupt.
RXFIFO_TOUT_INT_CLR

Set this bit to clear UART_RXFIFO_TOUT_INT interrupt.
SW_XON_INT_CLR

Set this bit to clear UART_SW_XON_INT interrupt.
SW_XOFF_INT_CLR

Set this bit to clear UART_SW_XOFF_INT interrupt.
GLITCH_DET_INT_CLR

Set this bit to clear UART_GLITCH_DET_INT interrupt.
TX_BRK_DONE_INT_CLR

Set this bit to clear UART_TX_BRK_DONE_INT interrupt.
TX_BRK_IDLE_DONE_INT_CLR

Set this bit to clear UART_TX_BRK_IDLE_DONE_INT interrupt.
TX_DONE_INT_CLR

Set this bit to clear UART_TX_DONE_INT interrupt.
RS485_PARITY_ERR_INT_CLR

Set this bit to clear UART_RS485_PARITY_ERR_INT interrupt.
RS485_FRM_ERR_INT_CLR

Set this bit to clear UART_RS485_FRM_ERR_INT interrupt.
RS485_CLASH_INT_CLR

Set this bit to clear UART_RS485_CLASH_INT interrupt.
AT_CMD_CHAR_DET_INT_CLR

Set this bit to clear UART_AT_CMD_CHAR_DET_INT interrupt.
WAKEUP_INT_CLR

Set this bit to clear UART_WAKEUP_INT interrupt.

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data